Programmable high speed frequency divider

Details Programmable high speed frequency divider Programmable high speed frequency divider

2001-09-13

2003-01-07

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C377S110000

Reexamination Certificate

active

06504407

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a frequency divider, and more particularly, to a programmable high speed frequency divider capable of programming the dividing ratio of an input clock frequency, in which the construction of flip-flops for forming the frequency divider is simplified in order to increase the operation speed of the frequency divider.
2. Description of the Related Art
Generally, in order to generate a signal of a desired frequency by using a clock signal in an electronic circuit, a circuit for dividing a clock signal frequency by an arbitrary natural number N is needed. This circuit is referred to as a frequency divider.
Here, N is a natural number equal to or greater than 2 and its maximum value differs depending on the number of bits in an implemented counter. Generally in a k-bit counter, N is set to be a value within a range defined by the following equation 1:
2
≦N
≦2
k
−1  (1)
FIG. 1
is a circuit diagram of a prior art 6-bit counter which is used in a frequency divider. Because k is
6
, the counter has 6 flip-flops, each having a set function and a reset function.
A clock signal which is desired to be divided is input to flip-flop (FF
11
) representing the least significant bit. The counter has an asynchronous structure in which the output signal of a flip-flop is the clock input of the next digit flip-flop. When a clock signal passes through bit-by-bit from the least significant bit to the most significant bit, the output frequency of each flip-flop decreases by half.
When the dividing ratio of an input clock signal is set to N, flip-flops (FF
11
-FF
16
) forming the counter are initialized to represent N by signals st
1
through st
6
and rst
1
through rst
6
which are generated in a control circuit
10
. For example, if N is
19
, i.e., the binary number
010011
, the six flip-flops (FF
11
-FF
16
) are set to represent the bits of the binary number in reverse order, i.e., the six flip-flops (FF
11
-FF
16
) are set to represent the bits 1, 1, 0, 0, 1, 0, respectively. To set a flip-flop to ‘1’, a set signal is applied to the flip-flop, and to set the flip-flop to ‘0’, a reset signal is applied to the flip-flop.
Whenever a clock signal is applied to the flip-flop representing the least significant bit (FF
11
), the number represented by the 6-bit counter (FF
11
-FF
16
) decreases gradually. If the number represented by the 6-bit counter (FF
11
-FF
16
) becomes ‘0’, N is again loaded into the flip-flops of the counter by a set or reset signal, and counting is carried out in the decreasing direction.
When N is loaded, a signal having a predetermined cycle is generated by the control circuit
10
of the counter. The generated frequency of this signal is the value obtained by dividing an input clock signal frequency by N.
FIG. 2
is a logic circuit diagram of the control circuit
10
for generating a set signal and a reset signal for loading N to flip-flops (FF
11
-FF
16
) of the counter shown in FIG.
1
.
As shown in
FIG. 2
, the control circuit
10
includes one flip-flop (FF
17
) and a plurality of NAND gates (G
13
and G
14
) and NOR gates (G
11
-G
15
). The function of a circuit formed by the NAND gates and NOR gates is receiving the outputs of the six flip-flops (FF
11
-FF
16
) and determining whether or not the value represented by the counter and taken from the flip-flop representing the most significant bit to the flip-flop representing the least significant bit of the counter is ‘000010’. If the counter represents ‘000010’, the circuit provides ‘1’ to the D input terminal of flip-flop FF
17
, and if not, the circuit provides ‘0’.
The output of flip-flop FF
17
is fed back to NAND gate G
14
in order to avoid providing an incorrect logical value to flip-flop FF
17
due to delay time by a logic circuit. Then, using the output signal of flip-flop FF
17
, the control circuit
10
generates set signals and reset signals for the respective flip-flops (FF
11
-FF
16
) forming the counter. For example, when a non-inverted output of flip-flop FF
17
is ‘1’, if a value to be loaded in an arbitrary flip-flop of the counter is ‘1’, ‘1’ is provided as a set signal for the flip-flop and ‘0’ is provided as a reset signal for the flip-flop. However, if a value to be loaded in an arbitrary flip-flop of the counter is ‘0’, ‘0’ is provided as a set signal for the flip-flop and ‘1’ is provided as a reset signal for the flip-flop.
In this way, in the counter used in a frequency divider, flip-flop FF
11
, which is located in the least significant bit among six flip-flops, operates at the highest frequency, and as the signal passes through the flip-flops to the flip-flop in the most significant bit, the maximum operating frequency decreases by half at each flip-flop. Therefore, flip-flops operating at higher frequencies must have simpler structures so they can operate at high speed.
However, according to the structure of a prior art counter used in a frequency divider, all flip-flops, including the flip-flop representing the least significant bit, are loaded with a desired dividing ratio using set signals and reset signals. As a result, the structure of the flip-flop representing the least significant bit is complex, the operating speed is relatively low, and therefore it is difficult to divide a clock signal with a higher frequency.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is an objective of the present invention to provide a programmable high speed frequency divider, in which for flip-flop representing the least significant bit among flip-flops forming a counter, the flip-flop having a simple structure, which does not use a set signal and a reset signal, is used in order to increase the operating speed of the frequency divider.
To accomplish the objective of the present invention, there is provided a programmable high speed frequency divider having a counter in which a clock signal desired to be divided is applied to the clock terminal of the first flip-flop representing the least significant bit; the output terminal of the flip-flop representing the least significant bit is connected to the clock terminal of the second flip-flop representing the next least significant bit, and the next flip-flops are connected in the same manner through to the highest effective digit flip-flop; the set terminal and reset terminal of the first flip-flop are open and a logical operation result of control signals and output signals of the flip-flops is applied to the input terminal of the first flip-flop; and all the flip-flops except the first flip-flop are initialized with cycles corresponding to a dividing ratio by set signals or reset signals; and a control circuit which receives the outputs of the flip-flops forming the counter, generates control signals corresponding to counting values of the counter with a predetermined logic gate circuit, and generates set signals and reset signals for initializing flip-flops forming the counter with cycles corresponding to the dividing ratio.


REFERENCES:
patent: 3774056 (1973-11-01), Sample et al.
patent: 4296380 (1981-10-01), Minakuchi
patent: 4741004 (1988-04-01), Kane

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