Programmable high performance data communication adapter for hig

Details Programmable high performance data communication adapter for hig Programmable high performance data communication adapter for hig

1994-06-01

1996-06-18

Chin, Wellington

Multiplex communications

Wide area network

Packet switching

3642389, 39520002, H04J 302, H04L 1256

Patent

active

055285872

ABSTRACT:
A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises

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Fujitsu-Scientific & Tech. Journal, vol. 23, No. 4, pp. 201-215 Dec./1987 "The Development Concept and Hardware Architecture of the ACOM M-780 Model group", Tone et al.
IBM TDB, vol. 33, No. 7, pp. 351-354. Dec./1990 "Queueing problem avoidance by using finite resource list".
Int. Conf. on Computer Design, 10-87, pp. 100-106, French et al., "An Eight Channel Synchronous Data controller for a primary rate Interface to ISDN".
SIGMOD'88, 8-88, pp. 134-145, Song et al, "Optimizing Bulk data Transfer performance: A packet Train Approach".
COMPCON '83, 3-83, pp. 510-517, Stark et al, "A High Functionality VLSI Ian controller for CSMA/CD Network".

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