Programmable gain amplifier circuitry and method for biasing JFE

Amplifiers – With semiconductor amplifying device – Including differential amplifier

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330282, 330296, H03G 330, H03F 345

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active

053270983

ABSTRACT:
A circuit for reducing input offset error and improving gain switching speed in a programmable gain amplifier includes a level shifting buffer that senses a signal on a common mode conductor in a differential input stage of an operational amplifier, and shifts the level of that signal up to the level corresponding to a level of an input signal applied to a non-inverting input of the operational amplifier. If a gain select signal is at a first logic level, the voltage produced by the buffer is applied to a gate electrode of one of a plurality of gain switching JFETs coupling a gain network to the inverting input of the operational amplifier, turning that JFET on. If the gain select signal is at a second logic level, the output of the buffer is isolated from the gain switching JFET and a turn off voltage is applied to the gate of the gain switching JFET.

REFERENCES:
patent: 4016557 (1977-04-01), Zitelli et al.
patent: 4393351 (1993-07-01), Gregorian et al.
patent: 4438354 (1984-03-01), Haque et al.
patent: 4500845 (1985-02-01), Ehni
patent: 4617481 (1986-10-01), Masuda
patent: 4855685 (1989-08-01), Hochschild

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