Programmable frequency divider in a phase lock loop

Details Programmable frequency divider in a phase lock loop Programmable frequency divider in a phase lock loop

1993-04-19

1994-10-25

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Comparing counts

377 47, 377 52, H03K 2102

Patent

active

053596358

ABSTRACT:
A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. A programmable divider latches a program integer for providing a latch integer, compares the latch integer to a constant integer, and generates a flag signal having a first state when the latch integer mismatches the constant integer and a second state when the latch integer matches the constant integer. The latch integer is decremented when the flag signal has the first state. The flag signal is delayed in response to first and second clock signals for providing the second digital signal having a frequency determined by the program integer. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal.

REFERENCES:
patent: 4573017 (1986-02-01), Levine
patent: 4882505 (1989-11-01), Furman
patent: 4937846 (1990-06-01), Malka et al.
patent: 5155748 (1992-10-01), Rabii
patent: 5221906 (1993-06-01), Hayashi et al.

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