Programmable frequency divider circuit

Details Programmable frequency divider circuit Programmable frequency divider circuit

1992-06-08

1994-09-20

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

With programmable counter

377 48, 377 50, H03K 2366

Patent

active

053496221

ABSTRACT:
A programmable frequency divider circuit includes a prescaler which consists of p cascade-connected dividing cells, a cell of rank i in the cascade having a normal division factor 2 and also being programmable so as to divide by 3 the input frequency applied to the cell. Each cell of rank i supplies, as a signal enabling the programmed mode for the preceding cell of rank i-1, a signal which is referred to as a gating signal and which is calibrated as regards duration and position in time at the operating frequency of the cell i, the prescaler (PPSC) being associated with counting means (CNT) for producing a programmable division factor (R) which is equal to M.2.sup.p +N, where M is an integer number applied to the counting means (CNT), p is the number of cells of the prescaler (PPSC), and N is an integer number applied to the programming inputs of the prescaler (PPSC).

REFERENCES:
patent: 4468797 (1984-08-01), Shin
patent: 4573176 (1993-11-01), Yeager
patent: 5065415 (1991-11-01), Yamashita

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