Programmable frequency divider and frequency dividing method...

Details Programmable frequency divider and frequency dividing method... Programmable frequency divider and frequency dividing method...

2011-07-05

2011-07-05

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S115000

Reexamination Certificate

active

07973575

ABSTRACT:
A programmable frequency divider, which is a core module of a frequency synthesizer using a Phase Locked Loop (PLL) for generating very high frequencies, includes a divided clock generator dividing a frequency of an input clock signal Finby a first divide ratio (N+1) or a second divide ratio N according to a divide ratio control signal MC to generate a plurality of divided clock signals Dout; a counting unit counting the number CNT of the plurality of divided clock signals Dout, by performing swallow mode counting and program mode counting sequentially on the plurality of divided clock signal Dout; a control signal generator generating the divide ratio control signal MC, using the number CNT of the plurality of divided clock signal Dout, a count S by the swallow mode counting and a count P by the program mode counting, the count P corresponding to a maximum of the number CNT, feeding the divide ratio control signal MC back to the divided clock generator, and generating a reset control signal RST for resetting the counting unit.

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Rabaey, Jan. M., et al. “Digital Integrated Circuits—A Design Perspective”, Second Edition, Prentiss Hall Electronics and VLSI Series, Cover and p. 215.

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