Programmable frequency divider

Details Programmable frequency divider Programmable frequency divider

2007-06-12

2007-06-12

Le, Dinh T. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S044000

Reexamination Certificate

active

11291071

ABSTRACT:
A programmable frequency divider capable of operating in a normal mode and a fractional mode divides the input clock frequency by any integer ‘N’ provided at the input. In the normal mode the input is divided by the integer ‘N’. The divided output signal has a 50% duty cycle if the input clock has a 50% duty cycle. In the fractional mode, fractional division can be achieved from dividing by 1.5 to dividing by 255.5 in steps of 0.5.

REFERENCES:
patent: 4975931 (1990-12-01), Cosand
patent: 5396109 (1995-03-01), Oshiba
patent: 5694089 (1997-12-01), Adachi et al.
patent: 6114915 (2000-09-01), Huang et al.
patent: 6236278 (2001-05-01), Olgaard
patent: 6445760 (2002-09-01), Weintraub et al.
patent: 6795519 (2004-09-01), Chakravarthy

Affiliated with

Also associated with

Rating

Programmable frequency divider does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable frequency divider, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable frequency divider will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3860908