Programmable frequency divider

Details Programmable frequency divider Programmable frequency divider

2005-11-29

2005-11-29

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C377S047000, C377S048000

Reexamination Certificate

active

06970025

ABSTRACT:
Various apparatus and method embodiments are disclosed. One apparatus embodiment, among others, comprises a frequency divider configured to provide an output signal having a period equal to a period of a clock signal multiplied by a programming division ratio, the frequency divider comprising a plurality of edge-triggered storage elements arranged in at least one loop, wherein each of the storage elements has a state, and a clock input, and wherein the state of each storage element is determined responsive to a transition of the clock input, the state, or the inverse thereof, of one or more previous storage elements in the loop, a characteristic of the division ratio, and the previous state, or the inverse thereof, of the storage element, and the output signal is derived from the state, or the inverse thereof, of at least one of the storage elements in the loop, a circuit for determining the number of storage elements in the loop responsive to the desired division ratio, and wherein the loop is configured such that there are odd number loop inversions within the loop, the loop inversions are implemented through inverters, and each of the storage elements is configured to enter a power save mode responsive to assertion of a power control signal.

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U.S. Patent Application entitled, “Frequency Divider with Low Harmonics,”Ser. No. 09/821,833, filed on Mar. 30, 2001.

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