Programmable frequency divider

Details Programmable frequency divider Programmable frequency divider

2000-02-24

2001-08-28

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000, C327S147000

Reexamination Certificate

active

06281721

ABSTRACT:

TECHNICAL FIELD
This invention relates to programmable frequency dividers and frequency synthesizers.
BACKGROUND OF THE INVENTION
It is well known that programmable frequency dividers are commonly used in phase-lock-loop (PLL) frequency synthesizers, such as for generating a local oscillating signal in a receiver or a carrier signal in a transmitter. One conventional type of programmable frequency divider is a phase-switching-type frequency divider which includes a) a prescaler which divides the frequency of an input waveform,f
in
, by two, b) a divide-by-two circuit which divides the frequency of the prescaler output by two and outputs four phase-offset versions of f
in
/4− offset by 0°, 90°, 180°, and 270° respectively, c) a multiplexer for selectively switching between the four outputs of the divide-by-two circuit, d) a divide-by-N circuit for dividing the frequency of the waveform output by the multiplexer by N, e) a pulse generator for generating K pulses per output cycle of the frequency divider, f) a four-state counter for incrementing after each pulse of the pulse generator, and g) a decoder for controlling the multiplexer based on the four-state counter output. To swallow one cycle of f
in
and thereby increase the division factor of the frequency divider by one, the multiplexer switches to an output of the divide-by-two circuit which lags the previously selected output by 90°. If the decoder controls the multiplexer to switch to a 90° lagging output K times per output cycle of the frequency divider, i.e., each time the counter increments, K input cycles are swallowed and the division factor becomes 4N+K To achieve programmability, the pulse generator must be able to generate various numbers of pulses each output cycle, depending on K. Designing and programming such a pulse generator is complicated. Also, for large values of K, the pulse generator, the divide-by-four counter, and the decoder must operate at high frequencies, thereby increasing power consumption.
SUMMARY OF THE INVENTION
We have recognized that the design and programming complexity associated with conventional frequency divider configurations can be significantly reduced in accordance with the principles of the invention, in which a programmable frequency divider includes a chain of functionally identical, modular division blocks which are each able to swallow at least one input cycle by switching to a phase-lagging output once per output cycle. The number of input pulses swallowed when a division block switches to a phase-lagging waveform is a direct function of the division block's location in the chain, such that the number of input cycles swallowed per phase switch increases moving down the chain of division blocks. Therefore, the chain of division blocks has discrete elements for achieving most-significant to least-significant division factor increments, and the total number of input cycles swallowed by the chain of division blocks equals the sum of cycles swallowed by each division block. Thus, to achieve a variety of division factors, a controller controls which, if any, division blocks switch to a phase-lagging waveform once each output cycle.
In one exemplary embodiment of the invention, a frequency divider includes a divide-by-two prescaler, a chain of functionally identical, modular divide-by-two blocks following the prescaler, and a controller. Each divide-by-two block includes a divide-by-two circuit which outputs four waveforms that are offset by 0°, 90°, 180°, and 270° respectively, and a multiplexer which selects one waveform output based on a control signal received from the controller. Control bits b
M
, . . . , b
0
are set according to the desired division factor and converted by the controller to a multiplexer control signal for each divide-by-two block. Division factors varying from 2
M+2
to 2
M+2
+2
M+1
−1 can be achieved using a chain of M+1 division blocks by setting each control bit b
M
, . . . , b
0
to either 1 or 0.
We have further recognized that switching to a phase-leading waveform will shorten a pulse of a waveform, and that the controller can control a divide-by-two block to switch to a phase-leading waveform once per output cycle to achieve certain division factors which are less than 2
M+2
. Therefore, a frequency divider structure with M+1 divide-by-two blocks can achieve division factors that are less than 2
M+2
, but which cannot be achieved with a frequency divider structure with less than M+1 divide-by-two stages. Setting a control bit b
MR
to 1 or 0 instructs the controller to selectively control the multiplexer of the last divide-by-two block to switch to a phase-leading waveform each output cycle.
Advantageously, various division factors may be readily achieved according to the principles of the present invention by selecting a number of division blocks, deciding whether the last division block should switch to a phase-leading output once per output cycle, and determining which, if any, division blocks should switch to a phase-lagging output once per output cycle. In this way, the frequency divider of the present invention is scalable and easily programmable, and does not require a pulse generator to control phase switching. Furthermore, because each multiplexer switches to a different output at most once per output cycle, most elements of the frequency divider operate at relatively low frequency, thereby reducing power consumption.


REFERENCES:
patent: 5781054 (1998-07-01), Lee
patent: 6052034 (2000-04-01), Wang et al.
patent: 6111470 (2000-08-01), Dufour
A Low Power Truly-modular 1.8GHz Programmable Divider in Standard CMOS Technology, Cicero Vaucher and Zhenhua Wang, Philips Research Labs Eindhoven, Philips Semiconductors Zurich, pp. 406-409.
A 5.3 GHz Programmable Divider for HiPerLAN in 0.25&mgr;m CMOS, N. Krishnapura, P. Kinget, Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA, pp. 142-145.

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