Programmable filter architecture

Details Programmable filter architecture Programmable filter architecture

2005-08-30

2005-08-30

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S320000

Reexamination Certificate

active

06938063

ABSTRACT:
A filter (50) with interconnected modular basic units (10) and with a delay line (51), equipped with takeoff points, to furnish delayed sampling values (x1, . . . , xN; xi) of a digital signal (x). Each basic unit (10) contains a programmable weighting device (11, 12), a linkage device (13, 14), and a delay device (15), which delays the data conducted to it by a single period (T) of the sampling clock pulse or by a simple integer multiple thereof. The filter (50) further contains a programmable control device (52), which switches over or switches off a part of the data inputs (16, 17) of the basic unit (10) to achieve forward and/or backward filtering and/or sign inversion and/or a change of the active filter length.

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patent: 5790439 (1998-08-01), Yamanaka et al.
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