Programmable error-checking matrix for digital communication sys

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371 48, 395200, G06F 1100

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053965051

ABSTRACT:
A programmable system for checking for protocol errors in a communication system includes a matrix for generating error checking signals selected by data fields utilized to implement a communication. If the configuration or protocol is changed the system facilitates reprogramming to compensate for the change.

REFERENCES:
patent: 4418384 (1983-11-01), Holtey et al.
patent: 4545055 (1985-10-01), Patel
patent: 4646300 (1987-02-01), Goodman et al.
patent: 4908823 (1990-03-01), Haagens et al.
patent: 4932023 (1990-06-01), Geyer et al.
patent: 4939735 (1990-07-01), Fredericks et al.
patent: 4975882 (1990-12-01), Kuo et al.
patent: 4991133 (1991-02-01), Davis et al.
patent: 5007051 (1991-04-01), Dolkas et al.
patent: 5128945 (1992-07-01), Enns et al.
patent: 5206952 (1993-04-01), Sundet et al.
patent: 5271020 (1990-12-01), Marisetty
patent: 5293384 (1994-03-01), Keeley et al.
patent: 5307179 (1994-04-01), Yoshida

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