Programmable edge defined output buffer

Details Programmable edge defined output buffer Programmable edge defined output buffer

1984-11-15

1986-10-07

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307453, 307468, 307269, H03K 17693

Patent

active

046161473

ABSTRACT:
A programmable edge defined output buffer clocks a first logic state to a first node when an input signal is in a first condition and a second logic state to a second node when the input signal is in a second condition. A programmable coupling circuit is programmable to couple the first and second nodes to an input of an amplifier. The programming selection determines in response to which signals will the first and second nodes be coupled to the input of the amplifier.

REFERENCES:
patent: 4084105 (1978-04-01), Teranishi et al.
patent: 4204131 (1980-05-01), Dozier
patent: 4469964 (1984-09-01), Guttag et al.
patent: 4482822 (1984-11-01), Kamuro et al.
patent: 4525640 (1985-06-01), Boyle et al.
patent: 4568841 (1986-02-01), Mayhew
Rutherford, "Time Division Multiplex Modulator for Multiphase Dynamic FET Logic", IBM T.D.B., vol. 14, No. 7, 12-1971, p. 1982.
Cordaro et al, "Programmable On-Chip Clock Generator", IBM T.D.B., vol. 17, No. 4, Sep. 1974, pp. 1051-1052.

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