Programmable driving power of a CMOS gate

Details Programmable driving power of a CMOS gate Programmable driving power of a CMOS gate

1992-01-02

1993-06-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307594, 307602, H03K 19094, H03K 1920

Patent

active

052202160

ABSTRACT:
A CMOS gate is provided which has a programmable driving power characteristic so that its propagation delay time can be varied by digital select control signals (S1-Sm). The CMOS gate includes a programmable inverter section (12) formed of a plurality of inverters (12a-12m), a switching logic control section (14), and a static inverter (16). The switching logic control signal section is responsive to the digital select control signals for selectively programming a certain number of the plurality of inverters to be enabled. In this manner, a certain number of the plurality of inverters will be wired in parallel with the static inverter in order to produce the desired amount of propagation delay time.

REFERENCES:
patent: 4593203 (1986-06-01), Iwahashi
patent: 4719369 (1988-01-01), Asano et al.
patent: 4806804 (1989-02-01), O'Leary
patent: 4899071 (1990-02-01), Morales
patent: 5012141 (1991-04-01), Tomisawa
patent: 5118971 (1992-06-01), Schenck

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