Programmable divider exhibiting a 50/50 duty cycle

Details Programmable divider exhibiting a 50/50 duty cycle Programmable divider exhibiting a 50/50 duty cycle

1994-08-02

1995-04-25

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

377 39, 377 47, 327294, G06F 108

Patent

active

054106834

ABSTRACT:
A programmable clock divider in which a system reference clock signal is divided by a programmed integer value. A storage register stores a value equal to the desired divisor minus two. A stored value of zero results in a divide by two. The stored value is loaded into a compare register and a counter is implemented to count reference clock signals. The compare register value and the counter value are compared by a comparator logic circuit. When the two values are equal, a flip-flop is toggled to switch the prescale clock value output. The flip-flop control logic includes circuitry for ensuring that odd divides exhibit an output clock frequency having a 50/50 duty cycle by controlling the flip-flop toggle to coincide with system clock edges. The flip-flop control logic also controls the timing for loading and resetting the compare and counter logic, respectively.

REFERENCES:
patent: 3878370 (1975-04-01), Santomango et al.
patent: 4785415 (1988-11-01), Karlquist
patent: 4805199 (1989-02-01), Muramatsu
patent: 5221906 (1993-06-01), Hayashi et al.
patent: 5345489 (1994-09-01), Saitoh

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