Programmable divider circuit with a tri-state inverter

Details Programmable divider circuit with a tri-state inverter Programmable divider circuit with a tri-state inverter

1998-12-23

2000-10-17

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 1A, 331 8, 331 18, 327115, 327117, 327118, 377 52, H03L 716, H03K 2366

Patent

active

06133796&

ABSTRACT:
A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages. The circuit includes a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and wherein the second plurality M of transistor stages includes at least some of said first plurality N of transistor stages, including said first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the circuit operates as a divide-by-M circuit in which an output signal is generated which has one cycle for every M cycles of a clock signal applied to the transistor stages. The circuit includes a switching circuit having at least two inputs and arranged to selectively connect to the first stage, the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

REFERENCES:
patent: 3749937 (1973-07-01), Rogers
patent: 3958187 (1976-05-01), Suzuki et al.
patent: 4114049 (1978-09-01), Suzuki
patent: 4389728 (1983-06-01), Tsuzuki
patent: 4953187 (1990-08-01), Herold et al.
patent: 5425074 (1995-06-01), Wong
Suzuki et al., "Clocked CMOS Calculator Circuitry," IEEE Journal of Solid-State Circuits Dec. 1973, pp. 462-469.

Affiliated with

Also associated with

Rating

Programmable divider circuit with a tri-state inverter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable divider circuit with a tri-state inverter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable divider circuit with a tri-state inverter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-473097