Programmable digital signal processor using switchable unit-dela

Details Programmable digital signal processor using switchable unit-dela Programmable digital signal processor using switchable unit-dela

1993-04-30

1995-12-26

Mai, Tan V.

Boots, shoes, and leggings

G06F 1531

Patent

active

054793637

ABSTRACT:
A novel switchable unit-delay has been developed for the efficient implementation of programmable digital finite impulse response filters and correlators. A p-tap consisting of this novel switchable unit-delay and a two-non-zero-digit partial product generator and adder have been implemented. The combination of several p-taps, made possible by the switchable unit-delay, allows for the efficient implementation of coefficients with more than two non-zero digits. In a straightforward implementation of a programmable finite impulse response filter, many tap "multipliers" would significantly waste valuable computational resources since all filter taps would need to accommodate "difficult" coefficient values (i.e., many non-zero digits), while for any specific transfer function, most filter taps would not require such extreme capabilities. The switchable unit-delay not only allows the programing of the number of taps and the specific tap-coefficient values, it provides the capability for programing the optimal allocation of hardware resources to each filter tap.

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