Programmable digital signal delay device and its use for a error

Details Programmable digital signal delay device and its use for a error Programmable digital signal delay device and its use for a error

1990-05-30

1992-09-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 63, 328 72, 307595, 307597, 307602, 307603, 307605, 371 31, H03K 5159, H03K 700, H03K 1700, G06F 1100

Patent

active

051500663

ABSTRACT:
A programmable digital signal delay device for delaying a digital serial input signal SIN by a period .tau.=M.H. (where M is an integer H is the bit rate) and transforms SIN into a delayed output signal SOUT having the same bit rate, the number M being programmable in steps. The device includes an input register (4), a RAM (6) whose r bit locations contain p bits, an output register (8) and means for controlling the RAM which are formed by a decoder (11) which receives the number M, a cyclic counter (12) which receives a programming number N (or n) from the decoder whereby it cyclically addresses the RAM, and a sequencer (13) which supplies the RAM with the write and read control signals.

REFERENCES:
patent: 4001599 (1977-01-01), Karklys
patent: 4825109 (1989-04-01), Reynolds
Wyland, "Shift Register Can Be Designed Using RAMs and Counter Chips", EDN Jan. 5, 1974, pp. 64-67.

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