Programmable digital delay unit

Details Programmable digital delay unit Programmable digital delay unit

1995-09-21

1997-09-23

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327276, 327284, H03H 1126

Patent

active

056709048

ABSTRACT:
A programmable digital delay unit presenting a number of cascade-connected delay blocks, and a number of controlled bypass elements, one for each delay block. Each bypass element presents a bypass line and a multiplexer for selectively connecting the input or output of the respective delay block to the input of the next delay block. The delay blocks are formed by the cascade connection of flip-flops, and the number of flip-flops in each successive delay block, from the input of the delay unit, decreases in an arithmetic progression to the power of two, so that the selection signals for the respective multiplexers represent the bits of a digital word specifying the required delay.

REFERENCES:
patent: 4820944 (1989-04-01), Herlein et al.
patent: 4939677 (1990-07-01), Otuji et al.
patent: 5204559 (1993-04-01), Deyhimy et al.
patent: 5258660 (1993-11-01), Nelson et al.
patent: 5389843 (1995-02-01), McKinney
patent: 5459422 (1995-10-01), Behrim
Bazes, Mel, "A Novel Precision MOS Synchronous Delay Line," IEEE Journal of Solid-State Circuits SC-20(6):1265-1271, 1985.

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