Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-03-06
2002-12-31
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S218000
Reexamination Certificate
active
06501314
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to digital electronic circuitry, and more particularly to differential D flip-flop circuits for automatic test equipment applications.
BACKGROUND OF THE INVENTION
Differential flip-flops provide an important fundamental building block for digital systems. In some applications, differential flip-flops provide a temporary storage function. In other applications, such as automatic test equipment, differential flip-flops provide a way to synchronize data signals with timing signals to form a highly accurate timing generator.
As illustrated in
FIG. 1
, a conventional D-type differential flip-flop
10
typically includes respective master and slave cells
11
and
13
. The master cell employs a data set circuit
12
that receives differential data on the occurrence of a first clock edge from a clock input circuit
14
. On a subsequent edge of the clock signal, the data from the data set element is loaded and temporarily stored in a data store circuit
16
. On the same clock edge, the data in the data store circuit is provided as the differential input data for the slave cell
13
. The data set circuit is typically loaded by an input load circuit (represented by resistors R
1
and R
2
).
With continued reference to
FIG. 1
, the slave cell
13
is constructed similar to the master cell
11
, with its data set circuit receiving the output from the master cell and generating the differential output for the flip-flop
10
. Respective master and slave current sources
22
and
24
provide a fixed bias current for the master and slave cells. A more detailed description of this conventional construction is provided in U.S Pat. No. 6,140,845, to Benachour.
In one automatic test equipment application, the differential D flip-flop is implemented at the front end of a timing generator circuit
18
, with the clock input circuit
14
receiving signals from a system clock
19
. Timing data signals from a pattern generator
20
feed differential data to the complementary flip-flop data input. The output of the flip-flop drives a delay line
21
. Typically, the delay line includes several identical delay stages
23
, each having input data circuitry
25
in the form of a differential pair of transistors (not shown), and load circuitry
26
defined by a plurality of load transistors (not shown) to establish a predefined delay cell D.
Conventionally, the differential flip-flop delay is different from the delay line delay, often causing a substantial timing error. One of the major reasons for the error is the mismatch between the delay element load circuitry
26
and the flip-flop input load circuitry (R
1
, R
2
). This timing error may, in some circumstances, take more than half of an allowable timing error budget for high frequency applications. In some circumstances, further delay circuitry is implemented in an effort to address this problem. Unfortunately, the additional circuitry often takes the form of additional delay lines that adds to hardware costs, and uses valuable circuit area (chip space) and power.
What is needed and currently unavailable is a differential D flip-flop with a circuit construction that allows control over the flip-flop delay to maximize accuracy for the timing circuitry. The differential D flip-flop of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The programmable flip-flop of the present invention provides a programmable current source capability while implementing circuitry having delay characteristics similar to a delay-locked-loop (DLL) delay cell. In this manner, the flip-flop exhibits delay characterisitcs similar to the DLL delay cells that can be fine-tuned to track the DLL delays by programmably controlling the flip-flop bias current.
To realize the foregoing advantages, the invention in one form comprises a differential flip-flop including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell. The slave cell further includes a second current source having programmable inputs to vary the bias current in the slave cell, thereby controlling the delay characteristic of the flip-flop.
In another form, the invention comprises a timing circuit for use in automatic test equipment. The timing circuit includes a delay line having a plurality of delay elements for generating timing signals, each of the delay elements having delay load circuitry to generate a similar delay D. The circuit further includes a differential data source for generating timing data values, a differential system clock, and a differential D flip-flop. The differential D flip-flop includes a master cell having a fixed delay and respective master data and master clock inputs. The master data input is coupled to the data source and the master clock input is coupled to the differential system clock. The differential D flip-flop further includes a slave cell having respective slave data and slave clock inputs. The slave data input is coupled to the master cell differential output with the slave clock input inversely coupled to the differential system clock. The slave cell further includes a slave differential output and a programmable input to vary the delay of the slave differential output to match the similar delay D of each of the delay cells.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5001361 (1991-03-01), Tamamura et al.
patent: 5815019 (1998-09-01), Uemura et al.
patent: 5892382 (1999-04-01), Ueda et al.
patent: 5945858 (1999-08-01), Sato
patent: 6011431 (2000-01-01), Gilbert
patent: 6140845 (2000-10-01), Benachour
patent: 6218878 (2001-04-01), Ueno
patent: 6268752 (2001-07-01), Takahashi et al.
Kreisman Lance
Nu Ton My-Trang
Teradyne, Inc.
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