Programmable difference flag logic

Details Programmable difference flag logic Programmable difference flag logic

1992-07-31

1995-01-10

Callahan, Timothy P.

Communications: electrical

Digital comparator systems

307355, 36518901, G05B 100

Patent

active

053811267

ABSTRACT:
Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

REFERENCES:
patent: 4220990 (1980-09-01), Alles
patent: 4755988 (1988-07-01), Nelson et al.
patent: 4935719 (1990-06-01), McClure
patent: 5084841 (1992-01-01), Williams et al.

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