Programmable difference flag logic

Communications: electrical – Digital comparator systems

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

307355, 36518901, G05B 100

Patent

active

053811267

ABSTRACT:
Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

REFERENCES:
patent: 4220990 (1980-09-01), Alles
patent: 4755988 (1988-07-01), Nelson et al.
patent: 4935719 (1990-06-01), McClure
patent: 5084841 (1992-01-01), Williams et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable difference flag logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable difference flag logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable difference flag logic will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-853812

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.