Programmable deserializer

Details Programmable deserializer Programmable deserializer

2011-08-02

2011-08-02

Lauture, Joseph (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S101000

Reexamination Certificate

active

07990293

ABSTRACT:
A deserializer for converting serial data into at least one parallel data includes a first flip-flop group, a second flip-flop group and a programmable frequency divider. The first flip-flop group includes a plurality of flip-flops connected in series, where the first flip-flop group is controlled by a first clock signal. The second flip-flop group includes a plurality of flip-flops, where the second flip-flop group is controlled by a second clock signal, and the flip-flops of the second flip-flop group are respectively connected to output nodes of the flip-flops of the first flip-flop group. The programmable frequency divider is coupled to each of the flip-flops of the second flip-flop group, and is utilized for receiving a control signal and generating the second clock signal by performing a frequency-dividing operation according to a frequency-dividing factor set by the control signal.

REFERENCES:
patent: 6097323 (2000-08-01), Koga et al.
patent: 7626523 (2009-12-01), Shin et al.
patent: 7684763 (2010-03-01), Boos

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