Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
1998-02-24
2001-08-07
Wachsman, Hal (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S079000, C327S158000
Reexamination Certificate
active
06272439
ABSTRACT:
TECHNICAL FIELD
The present claimed invention relates to the field of frequency monitors. More particularly, the present claimed invention relates to programmable frequency monitors.
BACKGROUND ART
Digital system components are typically implemented in an integrated circuit (IC) chip. Within the IC chip, the operation of an IC is regulated by a system clock, which is one of the fundamental components of a digital system (e.g., computer system). The system clock signal is generally a rectangular pulse train or square wave. In a synchronous digital system, the system clock determines the exact times at which an output can change states. Hence, the output of a digital system depends largely on the accuracy and integrity of the system clock.
The integrity of the output depends largely on whether the system clock signal is generated in an operable or non-operable frequency. A system clock signal that is generated at a non-operable frequency causes internal timing problems that will affect the integrity of the output. Typically, a low frequency monitor is used to ensure that the system clock signal does not fall below a minimum acceptable operating frequency. Conversely, a high frequency monitor is used to ensure that the system clock signal does not rise above a maximum acceptable operating frequency. By using a low frequency monitor and a high frequency monitor in combination, the system clock signal is monitored to ensure that the clock signal is being generated within a window of valid operating frequencies.
Conventional frequency monitor circuits are designed to monitor only a specific frequency. Therefore, a low frequency monitor designed to monitor, for example, a clock signal having an anticipated low frequency of 8 MHz could not be used in a processor or other part in which the low operating frequency is for example, 2 MHz. Similarly, a conventional high frequency monitor designed to monitor, for example, a clock signal having an anticipated high frequency of 16 MHz would not be well suited for use with a processor or other part in which the high operating frequency is substantially higher than 16 MHz. Therefore, often when using conventional frequency monitors, a separate frequency monitor must be designed for each respective high and low operating frequency of each processor or part being monitored. It will be understood that conventional frequency monitor circuits require extensive redesign to realize different frequencies. Thus, conventional frequency monitors are extremely inflexible, are functionally limited, and can add significant additional design and implementation costs.
As yet another drawback, actual operating characteristics of conventional frequency monitors can also vary from the expected or intended operating characteristics. For example, even when the frequency monitor is designed to monitor a specific known frequency, process variations, operating conditions, and the like may alter the actual performance of the frequency monitor. Hence, even a “properly” designed frequency monitor can deviate from its intended operating characteristics in such a manner as to render the frequency monitor unreliable or useless.
As still another drawback, conventional frequency monitors are not able to precisely determine the actual low or high operating frequency of a given processor or part. More specifically, conventional frequency monitors are designed only to monitor a specific frequency, and do not quantitatively provide information as the current high or low operating frequency of the clock signal being monitored.
Thus, a need exists for frequency monitor which is not limited to solely monitoring a specific frequency. A further need exists for a frequency monitor which can readily monitor a variety of clock signal frequencies associated with various processors or integrated circuit parts. Still another need exists for a frequency monitor which is still reliable and is useful even when subjected to process variations and various operating conditions. Also, a need exists for a frequency monitor which can be used to determine the current operating frequency of a clock signal being monitored.
DISCLOSURE OF THE INVENTION
The present invention provides a frequency monitor which is not limited to solely monitoring a specific frequency. The present invention further provides a frequency monitor which can readily monitor a variety of clock signal frequencies associated with various processors or integrated circuit parts. The present invention also provides a frequency monitor which is still reliable and is useful even when subjected to process variations and various operating conditions. Also, the present invention provides a frequency monitor which can be used to determine the current operating frequency of a clock signal being monitored.
More specifically, the present invention provides a programmable low frequency monitor. In one embodiment, the present invention is comprised of a programmable delay circuit disposed in a low frequency monitor. The programmable delay circuit is adapted to programmably generate a selected delay. As a result, the frequency monitor can be configured to monitor a variety of operating frequencies. In the present embodiment, the programmable delay circuit is comprised of at least one delay cell which can be selectively activated or deactivated. A delay cell controller is coupled to the delay cell. The delay cell controller is adapted to selectively control whether the delay cell is activated. In so doing, the present embodiment achieves a frequency monitor which is programmably configurable to realize a selected delay.
In another embodiment, the present invention provides a high frequency monitor which utilizes the programmable delay circuit.
In still another embodiment, the present invention provides a method for determining the maximum operating frequency for a component. In this embodiment, the present invention programmably generates a reference clock signal having a frequency associated therewith. The programmably generated reference clock signal is then compared with an operating frequency of a component. If the programmably generated reference clock signal and the operating frequency of the component meet selected criteria, the frequency of the programmably generated reference clock signal is incrementally increased. Next, the programmably generated reference clock signal having the incrementally increased frequency is compared with the operating frequency of the component. In this embodiment, these steps are repeated until the programmably generated reference clock signal and the operating frequency of the component no longer meet selected criteria.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
REFERENCES:
patent: 5799049 (1998-08-01), McFarland et al.
patent: 5815016 (1998-09-01), Erickson
patent: 5910740 (1999-06-01), Underwood
patent: 5920216 (1999-07-01), Fischer
patent: 5923715 (1999-07-01), Ono
patent: 6081143 (2000-06-01), Ho et al.
Auer David A.
Buer Mark L.
VLSI Technology Inc.
Wachsman Hal
Wagner , Murabito & Hao LLP
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