Programmable delay of an interrupt

Details Programmable delay of an interrupt Programmable delay of an interrupt

1995-05-31

1998-01-13

Harvey, Jack B.

395733, G06F 1300

Patent

active

057088179

ABSTRACT:
A programmable interrupt delay in a communication circuit enables accurate timing of an interrupt delay without tying up processor CPU cycles in the execution of a delay loop. The interrupt delay comprises a memory containing the program delay value. A communication circuit which generates an interrupt output corresponding to the transmission of a communication data stream is coupled to a timing circuit having a time value. This timing circuit also has a timing start input, which triggers timing of the timing value upon receipt of the interrupt output. A comparator coupled to the memory and to the timing circuit compares the time value to the delay value and generates a delayed interrupt when the time value and the delay value are equal.

REFERENCES:
patent: 3789365 (1974-01-01), Jen et al.
patent: 5060239 (1991-10-01), Briscoe et al.
patent: 5247654 (1993-09-01), Hamid et al.
patent: 5363506 (1994-11-01), Fukuoka
patent: 5423049 (1995-06-01), Kurihara

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