Programmable delay locked loop

Details Programmable delay locked loop Programmable delay locked loop

2007-01-09

2007-01-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

11129681

ABSTRACT:
A delay lock loop (DLL) system includes a master DLL and at least one slave DLL. The master DLL comprises a master delay line, a phase detector, and a loop controller. The master delay line of the master DLL includes four quarter cycle delay lines (QCDL). The slave DLL comprises a delay line and a fractional bit delay element. The delay line of the slave DLL is controlled by the slave delay line control signal generated by the loop controller of the master DLL. The final output of the slave DLL is formed such that the output of the delay line of the slave DLL is corrected by the fractional bit delay generated by the factional bit delay element such that the final output of the slave DLL has a finer delay line resolution than the one of the output of the delay line of the slave DLL.

REFERENCES:
patent: 6373301 (2002-04-01), Chen et al.
patent: 6501312 (2002-12-01), Nguyen
patent: 6590434 (2003-07-01), Chung et al.
patent: 6791381 (2004-09-01), Stubbs et al.
patent: 6839860 (2005-01-01), Lin
patent: 6919750 (2005-07-01), Kawahito et al.
patent: 6999547 (2006-02-01), Braceras et al.
patent: 7030675 (2006-04-01), Wang et al.
patent: 7057429 (2006-06-01), Kim

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