Programmable delay line integrated circuit having programmable r

Details Programmable delay line integrated circuit having programmable r Programmable delay line integrated circuit having programmable r

1991-08-07

1992-09-01

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307605, 307608, 307597, 307494, 328 55, H03K 5159, G06G 712

Patent

active

051441730

ABSTRACT:
A programmable delay line with digital input to a two-part digital-to-analog converter structure to define an equivalent resistance at a pull-down node. Preferred embodiments are configured as two identical halves. The outputs of the two halves are combined to produce an exactly symmetrical waveform. This is particularly advantageous in a programmable delay line, since this architecture assures that control changes which change the delay will not also introduce asymmetry into the output waveform.

REFERENCES:
patent: 4742331 (1988-05-01), Barrow et al.
patent: 4845390 (1989-07-01), Chan
patent: 4899071 (1990-02-01), Morales

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