Programmable delay generator and application circuits having...

Details Programmable delay generator and application circuits having... Programmable delay generator and application circuits having...

1999-01-20

2001-02-13

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S105000, C327S107000, C327S116000, C327S172000, C327S156000, C327S131000, C327S122000, C708S276000

Reexamination Certificate

active

06188261

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a programmable delay generator, and an application circuit using said programmable delay generator. An application circuit includes a frequency synthesizer, a frequency multiplier, a duty ratio converter, and a PLL frequency synthesizer.
The present programmable delay generator provides an output pulse which is delayed by time defined by a predetermined digital data, from an input trigger pulse.
Further, the present invention provides a frequency multiplier which uses the present programmable delay generator, and provides output frequency having integer multiple frequency of input frequency. Further, the present invention provides a duty ratio converter which uses the present programmable delay generator and converts duty ratio of an input pulse to provide an output pulse having desired duty ratio.
FIG. 12
shows a prior programmable delay generator, which is shown in pages (12-36)-(12-64) in Linear Databook, 1994/1995, published by Analog Devices Co.
In
FIG. 12
, a current source
82
, a capacitor
83
and a switch
84
provide an integrator. A trigger circuit
81
opens or closes a switch
84
according to a leak signal
401
and a trigger signal
402
, and the integrator generates ramp wave voltage Vs. A latch circuit
85
latches a set data
404
responsive of a latch signal
403
, and an output of the latch circuit
85
is applied to a D/A (digital to analog) converter
86
. The D/A converter
86
provides threshold voltage Vk in analog form proportional to the set data
404
. A comparator
87
compares ramp wave voltage Vs with threshold voltage Vk, and provides an output pulse just when the former coincides with the latter. A one-shot multivibrator
88
receives an output of the comparator
87
, and provides an output pulse having a desired pulse width to an output terminal
405
.
FIG. 13
shows operational time charts of the programmable delay generator of FIG.
12
. In
FIG. 13
, a symbol for each signal coincides with a symbol in FIG.
12
. The curve (a) shows a trigger signal
402
, the curve (b) shows a latch signal
403
, the curve (c) shows a set data
404
, the curve (d) shows a leak signal
401
, the curve (e) shows a ramp wave voltage Vs across the capacitor
83
, the curve (f) shows a threshold voltage Vk which is an output voltage of the D/A converter
86
, and the curve (g) shows an output signal
405
which is an output of the one-shot multivibrator
88
, and is an output of the current programmable delay generator.
In
FIGS. 12 and 13
, a set data
404
is latched in the latch circuit
85
synchronized with the latch signal
403
. The D/A converter
86
provides a threshold voltage Vk in analog form proportional to the set data
404
. The threshold voltage Vk is expressed as follows, where V
0
is unit voltage of the D/A converter
86
, and K is a set data.
Vk=−KV
0
  (1)
A trigger signal
402
triggers the capacitor
83
to be charged by the current source
82
to generate ramp wave voltage Vs. The voltage of the ramp wave voltage Vs at time t is expressed as follows, where I is current of the current source
82
, C is capacitance of the capacitor
83
, and the trigger signal
402
rises at time t
0
.
Vs=−
(
I/C
)(
t−t
0
)  (2)
The comparator
87
detects that the ramp wave voltage Vs reaches the threshold voltage Vk. The time from t
0
until Vs reaches Vk, that is the delay time t
d
of the output signal
405
is shown as follows from the equations (1) and (2).
t
d
=(
KV
0
C
)/
I
  (3)
The output signal
405
falls when the time defined by time constant of the one-shot multivibrator
88
elapsed. And, the capacitor
83
is discharged by a leak signal
403
, so that ramp wave voltage Vs is again initialized.
As described above, the prior programmable delay generator of
FIG. 12
provides a delay time defined by a set data, as shown in the equation (3).
By the way, a programmable delay generator in which both a numerator and a denominator of a ratio are variable, is desired following the development of a frequency synthesizer. A fractional delay generator is essential to take a jitter free signal from an accumulator, and/or decrease spurious component in an output of a fractional N PLL frequency synthesizer.
However, a prior programmable delay generator of
FIG. 12
generates a delay time defined by the equation (3), therefore, although it can provide a delay time proportional to a set data K, it can not provide a delay time defined by a denominator. Further, a delay time depends upon the circuit constants V
0
, C and I as shown in the equation (3), and therefore, the accuracy of the circuit constants is essential to improve the accuracy of a delay time.
It should be noted in the equation (3) that the value I of a current source
82
is included in the denominator, this means that delay time depends upon denominator, however, the circuit constants V
0
, C and I must still be controlled to improve the absolute value of a delay time.
Further, when a frequency multiplier to provide integer multiple frequency of input frequency by supplying pulses having shorter period than that of input pulses, by using a conventional programmable delay generator, is desired, or a conversion of duty ratio for converting duty ratio of input pulse by determining interval between rise time and fall time of an output pulse by using a conventional programmable delay generator is desired, specific adjustment of circuit constants must be essential for each input frequency. Even when input frequency is determined, the circuit constants including V
0
, C, I are necessary to improve accuracy of delay time, if we use a conventional programmable delay generator.
Therefore, a prior programmable delay generator has a disadvantage that it is difficult to provide accurate delay time, and it can not be used in a frequency synthesizer which demands absolute accuracy of delay time.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a new and improved programmable delay time generator by overcoming the disadvantages and limitations of a prior programmable delay time generator.
It is also an object of the present invention to provide a programmable delay time generator which both numerator and denominator can be designed, and provides accurate delay time with no circuit adjustment.
It is also an object of the present invention to provide a frequency synthesizer which uses the present programmable delay time generator, and which provides spurious free output signal with no circuit adjustment.
It is also an object of the present invention to provide a frequency multiplier which provides spurious free multiplied output signal by using the present programmable delay time generator.
Further, it is an object of the present invention to provide duty ratio converter which provides accurate duty ratio of a pulse signal with no circuit adjustment, by using the present programmable delay generator.
The present programmable delay generator comprises; a first ramp wave generator and a second ramp wave generator, each having the same structure as each other, each of them operating with external common clock pulses, and each of them providing potential gradient and final potential incorporated with an external set data; a comparator for comparing an output (V
s
) of the first ramp wave generator and an output (V
k
) of the second ramp wave generator so that an output pulse is provided when the outputs of two ramp wave generators coincide with each other; said first ramp wave generator providing a first ramp voltage (V
s
) upon receipt of a first set data (S) at a predetermined time (t
0
); said second ramp wave generator providing a threshold voltage (V
k
) upon receipt of a second set data (K) at a time which preceds at least one clock time (T) than said predetermined time; said comparator providing an output pulse delayed by delay time (t
d
) which is proportional to ratio of said second set data and said first set data from said predetermined time.
In

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