Programmable delay for clock phase error correction

Details Programmable delay for clock phase error correction Programmable delay for clock phase error correction

2006-06-30

2009-06-09

Wells, Kenneth B (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S231000, C327S233000, C327S563000

Reexamination Certificate

active

07545194

ABSTRACT:
A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors of a first size, receiving the differential clock signal from the two clock signal lines into a second differential pair of transistors of a size smaller than the first size, converting the differential clock signal into a single-ended clock signal, outputting the single-ended clock signal through an inverter, and synchronizing any differential clock phase error by controlling the transconductance between the first differential pair of transistors and the second differential pair of transistors.

REFERENCES:
patent: 4866397 (1989-09-01), Kimyacioglu
patent: 5469120 (1995-11-01), Nguyen et al.
patent: 5635878 (1997-06-01), Liu et al.
patent: 6252432 (2001-06-01), Freitas
patent: 6433637 (2002-08-01), Sauer
patent: 6621317 (2003-09-01), Saeki
patent: 2003/0002607 (2003-01-01), Mooney et al.
patent: 2004/0120437 (2004-06-01), Casper et al.
patent: 2006/0181320 (2006-08-01), Dreps et al.
Razavi, B., et al.: “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, pp. 296, Figure 9.6 (3 pages), ISBN 0-07-238032-2, 2002.
United Kingdom Search Report for Application No. GB0712815.0, dated Oct. 9, 2007, 1 page.

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