Programmable delay device

Details Programmable delay device Programmable delay device

1982-02-16

1984-11-13

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307494, 307594, H03K 5159

Patent

active

044828268

ABSTRACT:
A programmable delay circuit is formed of at least one channel of cascaded, directly coupled inverter elements, the at least one channel including a power supply terminal to which a controllable operating voltage is supplied. The overall time delay exhibited by the at least one channel is a function of the magnitude of the operating voltage supplied to the power supply terminal and the number of cascaded inverter elements included therein. A desired time delay may be established by generating a voltage representing the actual time delay exhibited by the channel, comparing the generated voltage and a reference voltage representing the desired delay, and adjusting the magnitude of the operating voltage supplied to the power supply terminal as a function of the difference between the compared voltages. In a preferred embodiment, the programmable delay circuit includes at least one data channel and a reference channel, the reference channel being used to generate the aforementioned voltage representing the actual time delay exhibited by the at least one data channel.

REFERENCES:
patent: 3673438 (1972-06-01), Lund
patent: 3976893 (1976-08-01), Banfi
patent: 4129792 (1978-12-01), Kawagai et al.
patent: 4296338 (1981-10-01), Thomas
patent: 4339672 (1982-07-01), Sato
patent: 4379974 (1983-04-01), Plachmo
Richman, P., Characteristics and Operation of MOS Field Effect Devices, McGraw-Hill, 1967, pp. 114-118.

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