Programmable delay clock gaters

Details Programmable delay clock gaters Programmable delay clock gaters

2001-03-22

2002-10-01

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S108000, C327S112000, C326S095000, C326S098000

Reexamination Certificate

active

06459318

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to clock buffer circuits used in VLSI integrated circuits, and, more particularly to a qualified non-overlapping clock generator/buffer.
BACKGROUND OF THE INVENTION
Qualified non-overlapping generators (also known as clock gaters) may be used to prevent data from “racing” from one latch to another thereby causing errors. Non-overlapping clock signals generated by clock gaters are typically clock signals which one clock signal has a rising edge that occurs after a falling edge of the other clock signal and a falling edge that occurs before a rising edge of the other clock signal. Such clock signals prevent races through latches by deactivating a subsequent stage before data is allowed to propagate through the current stage.
Several versions of clock gaters, and their use in an overall clocking scheme, have been presented in U.S. Pat. No. 5,124,572 to Mason et al., U.S. Pat. No. 5,306,962 to Lamb, U.S. Pat. No. 5,726,596 to Perez, U.S. Pat. No. 5,760,610 to Naffziger, and U.S. Pat. No. 5,701,335 to Neudeck. These documents are all hereby incorporated herein by reference.
One of the design tradeoffs encountered when using clock gaters involves the amount of time that both clocks are inactive (i.e. non-overlapping). This is also referred to as dead time. Decreasing the amount of dead time may increase the frequency of operation of the integrated circuit (IC) by allowing more time for circuits to evaluate when at least one clock is active. However, this decreased dead time also increases the risk that the circuit will have some timing errors due to unforeseen delays or race conditions in the design of the IC. With larger dead times, it is less likely that an unforeseen delay or race condition will cause errors.
Increasing the amount of dead time decreases the likelihood that unforeseen delays or race conditions will cause errors. However, the increased dead time reduces the amount of time available during a clock phase for circuitry to evaluate. This decreases the performance of the integrated circuit by requiring lower clock frequencies to provide the same amount of evaluate time per clock phase. These tradeoffs are typically made during the design of the integrated circuit and therefore typically require a re-design of the clock gaters and re-fabrication of the entire chip to increase or decrease dead time thereby getting the chip to function properly or improve performance, respectively.
Accordingly, there is a need in the art for a reduced cost way of manipulating the amount of dead time provided by clock gaters. The amount of dead time should be able to be manipulated on a circuit-by-circuit basis without having to re-design every clock gater and re-fabricate the entire chip from scratch.
SUMMARY OF THE INVENTION
The invention provides a non-overlapping clock generator that has its dead time adjustable without a complete re-design and re-fabrication. Certain terminals of certain devices of the non-overlapping clock generator are connected only by metal layers. This allows the circuit of the non-overlapping clock generator to be changed, adjusting the dead time, by changing only the masks used to fabricate the metal layers. This allows non-overlapping clock generators on wafers that have been partially fabricated to have their dead times altered from the original design.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 4692637 (1987-09-01), Shoji
patent: 4992682 (1991-02-01), Asano et al.
patent: 5041738 (1991-08-01), Walters, Jr.
patent: 5124572 (1992-06-01), Mason et al.
patent: 5306962 (1994-04-01), Lamb
patent: 5418179 (1995-05-01), Hotta
patent: 5543736 (1996-08-01), Gardner et al.
patent: 5576654 (1996-11-01), Shu et al.
patent: 5701335 (1997-12-01), Neudeck
patent: 5726596 (1998-03-01), Perez
patent: 5748019 (1998-05-01), Wong et al.
patent: 5760610 (1998-06-01), Naffziger
patent: RE36469 (1999-12-01), Wood et al.

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