Programmable delay circuit

Details Programmable delay circuit Programmable delay circuit

1987-11-23

1988-05-17

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307597, 328 55, H03K 513, H03K 5159

Patent

active

047453109

ABSTRACT:
A monolithically integrated delay circuit is provided that comprises a gate coupled for receiving a digital input signal. The output of the gate is capacitively loaded whereby the output signal has a sloping downward transition. A line receiver has a first input coupled to said gate and a second input coupled for receiving an analog signal for comparing the analog signal with the output of the gate and for providing a digital output signal that is delayed with respect to the digital input signal.

REFERENCES:
patent: 4234850 (1980-11-01), Collins
patent: 4458165 (1984-07-01), Jackson
patent: 4504749 (1985-03-01), Yoshida

Affiliated with

Also associated with

Rating

Programmable delay circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable delay circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable delay circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1883048