Programmable delay circuit

Details Programmable delay circuit Programmable delay circuit

1989-05-05

1991-07-02

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307268, 307263, 307601, 307356, H03K 513, H03K 5159

Patent

active

050288245

ABSTRACT:
A low power programmable delay circuit produces an output pulse having multiple-variable signal characteristics that are independent of power supply functions and wafer processing parameters. The delay circuit employs a timing pulse generator which initiates the generation of a timing pulse in accordance with a prescribed logical combination of an input pulse and a control logic level. The timing pulse generator contains a time constant control circuit that establishes the rate of change of the leading and trailing edges of the timing pulse. The timing pulse is coupled to a Schmitt trigger circuit to produce a pulse having sharply defined leading and trailing edges the times of occurrence of which are determined by the trigger threshold of the Schmitt trigger circuit. This Schitt trigger output pulse is logically combined with the original input signal to produce a programmably delayed output pulse. The Schmitt trigger circuit is preferably comprised of a MOSFET comparator circuit and associated controlled latch voltage reference circuit. The source voltages for each arm of the comparator and those of voltage reference circuit are the logic levels of the digital signals being processed. As a result any fluctuation of the source voltages creates the same differential to both the comparator and the threshold reference networks, so that the Schmitt trigger operates independently of the voltage variation.

REFERENCES:
patent: 3760280 (1973-09-01), Covington
patent: 3790821 (1974-02-01), Adamson
patent: 4039858 (1977-08-01), Stewart
patent: 4620312 (1986-10-01), Yamashital
patent: 4694198 (1987-05-01), Umeki
patent: 4694208 (1987-09-01), Szabo et al.
patent: 4754477 (1988-06-01), Tanaka et al.
patent: 4812676 (1989-03-01), Yang et al.
patent: 4833346 (1989-05-01), Marple

Affiliated with

Also associated with

Rating

Programmable delay circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable delay circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable delay circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1249170