Programmable delay cell

Details Programmable delay cell Programmable delay cell

2000-01-31

2002-03-12

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S277000, C327S299000, C327S269000

Reexamination Certificate

active

06356132

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to signal paths and, in particular, to the use of delay cells to achieve desired delays in clock and/or data signal paths.
2. Description of the Related Art
Circuits such as integrated circuits (ICs) typically contain signal paths for providing a given signal, such as a digital signal, from a particular signal source to a particular signal sink. For example, digital ICs typically provide both data signals and clock signals on data and clock signal paths, respectively (data signals may be considered to also include address, control, or any other type of non-clock signals, for purposes this application). A flip-flop, for example, of a memory array, may receive a clock signal from a clock signal source via a clock signal path of a clock tree, and may also receive data signals from a data source, such as a processor, via a data signal path. ICs are circuits typically formed in a manufacturing process on silicon wafers which provide a common substrate for the components of the ICs.
Clock signals are regularly timed periodic signals, which are often utilized for timing and other purposes in circuits or systems, such as digital circuits, which are often implemented as ICs. These clock signals are generated by clock sources or drivers either internal and/or external to the circuit. For example, a fast type of external clock source may be a crystal-based clock or a phase-locked loop (PLL) clock. An internal clock may be a slower, crystal-based clock or a ring oscillator. A clock signal is typically a square wave, i.e., a signal which is virtually always at either a logic “0” or low value (e.g., 0V or V
SS
) or a logic “1” or high value (e.g., 3.0V or V
DD
), with sharply defined edges at transition times. A clock signal thus contains a series of rising (positive) and falling (negative) edges, when the clock signal transitions from low to high and vice-versa. Data signals, while not typically periodic square waves, have similar characteristics, in that the data bits transition from logic 0 to logic 1 and vice-versa.
ICs typically include a clock network for providing a clock signal to various synchronized circuitry. The clock network typically includes one or more clock sources that are coupled to one or more clock “sinks.” A clock sink is any circuit or other system element requiring a clock. Examples of clock sinks include flip-flops, Latches, registers, and gates. A clock signal may be used to trigger such elements in digital circuits. For example, storing data into a register might be triggered by the rising edge of the clock signal, i.e., the transition from low to high (a rising edge). Many digital circuits (clock sinks) are “edge-triggered,” i.e., triggered by either the rising or falling edges of the clock signal.
The timing of clock and data signals in ICs is often critical and needs to be precisely controlled. Thus, the delay faced by a given data or clock signal over its respective signal path, from the signal source to the signal sink, needs to be taken into account. For example, the path length, resistance, number and type of drivers, parasitic capacitance, and other characteristics of a given signal path affect the delay between source and sink via the path.
For example, to write data to a flip-flop, it is typically desirable that data signal transitions arriving at the data input terminal of the flip-flop (data sink) arrive outside the time window between the set-up and hold time—i.e., the data transitions at the flip-flop occur after the hold time after the clock edge triggers, and before the set-up time before the next clock transition. Therefore, the IC designer tries to ensure that clock and data signal path relative delays are such that clock signals are properly aligned with respect to corresponding data signals.
Also, with regard to clock signals themselves, for example, it is typically desired that clocks routed within the IC be synchronized, such that each clock sink receives the same clock signal at approximately the same time. If clock signals arrive at various clock sinks at different times, this results in “clock skew” at the clock sinks, which can impair synchronization. Thus, in many synchronous digital circuits, the clock edges of the clocks for various circuit regions are aligned to occur, ideally, at the same time throughout the system. The IC designer attempts to achieve this by ensuring that the various clock paths of a given clock network or clock tree have the same signal delay.
A clock tree distributes an input clock signal from a given source to various clock sinks in the system, by a network of clock drivers and clock signal paths from the clock source to the clock sinks to be driven by the clock signal. Thus, for example, a given clock tree may have three branches for distributing a clock signal provided by a single clock source to three (or more) different clock sinks. Each branch is designed so that each clock signal propagating therethrough is delayed by the same amount from the common point of the branches (e.g., the clock source) to the various clock sinks.
It can be difficult to precisely determine, at the design stage, the delay of various signal paths in the IC, due to the complex factors that influence the signal delay. Often an IC will be fabricated, and testing determines that the delays of one or more paths are too long or too short. For example, if the delay of a clock path for a flip-flop is longer than expected from the IC design and layout, the data signal may transition too early, before the hold is completed. In such a case it would be desirable to increase the relative delay of the data signal path (or, what is the same thing, to decrease the relative delay of the clock signal path).
Conventional responses to this problem include redesigning the IC or its layout. For example, signal path routing may be changed, in an attempt to adjust the delays to within acceptable limits. However, this can be expensive and time-consuming. Alternatively, instead of redesigning the entire layout, only the metal masks are changed to re-route wires. This latter approach is typically less costly than the former approach, but can still be prohibitively or undesirably expensive and time-consuming.
SUMMARY
In the present invention, an integrated circuit has a plurality of signal paths, at least one of which has a delay cell. The delay cell has an input terminal for receiving an signal from the signal path, and a plurality of delay paths for generating a corresponding plurality of delayed signals delayed by different delays from the input signal. At least one of the delay paths employs two different-delay subpaths coupled in parallel to provide a delayed signal delayed by an interpolated delay. A multiplexer (MUX) of the delay cell provides one of the delayed signals as an output signal to the signal path based on a control input signal applied to the multiplexer.


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