Programmable data sampling receiver for digital data signals

Details Programmable data sampling receiver for digital data signals Programmable data sampling receiver for digital data signals

2011-07-19

2011-07-19

Ha, Dac (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C327S052000, C327S089000, C327S096000, C327S127000, C327S246000, C330S250000, C330S252000, C375S318000, C713S401000

Reexamination Certificate

active

07983362

ABSTRACT:
Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.

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