Programmable data processor for use in small and medium-size swi

Details Programmable data processor for use in small and medium-size swi Programmable data processor for use in small and medium-size swi

1977-10-12

1979-05-22

Brown, Thomas W.

H04Q 354

Patent

active

041561139

ABSTRACT:
A data processor for a telecommunication system comprises a program and data memory ME controlled by a block MEV including address registers C1, C2, an address store ACT and an instruction counter US, the memory exchanging information with the components of block MEV and with a set of working registers REG via a reading bus l.sub.rl and a writing bus l.sub.w ; another reading bus l.sub.r2 interlinks some of the aforementioned components. An associated execution unit includes an instruction register U divided into two sections MR and UR receiving instruction words from the writing bus, these words consisting of a group of operand bits fed from section UR to a microprogrammed command-signal generator MV and a group of transformation bits fed from section MR to an address store MC. The signal generator MV emits commands for the transfer of addresses from block MEV to memory ME as well as for the readout of data from that memory to an arithmetical unit ALU also receiving data from registers REG, unit ALU being controlled by the contents of store MC; the latter is divided into a plurality of fields all containing the same number of operating instructions (here four) selectable by the transformation bits from register section MR while the field is identified by a bit group received from signal generator MV. Instruction counter US includes two counting registers, P1, P2 connected in parallel between the writing bus l.sub.w and the reading bus l.sub.rl, the first counting register P1 being stepped by commands from generator MV and having another output which works under the control of that generator into a counting input of the second counting register P2 also having an output connection to the internal bus l.sub.r2. Address store ACT includes two data-page registers Y1, Y2 with inputs connected to the writing bus l.sub.w and outputs connectable in a predetermined sequence, via a switching network Y.sub.K, to the internal bus l.sub.r2.

REFERENCES:
patent: 3497630 (1970-02-01), Lucas et al.
patent: 3582896 (1971-06-01), Silber
patent: 3665510 (1972-05-01), Brandt et al.
patent: 3775754 (1973-11-01), Auspurg et al.
patent: 3965458 (1976-06-01), Borbas et al.

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