Programmable data path width in a programmable unit having plura

Details Programmable data path width in a programmable unit having plura Programmable data path width in a programmable unit having plura

1988-10-24

1991-07-23

Lee, Thomas C.

Boots, shoes, and leggings

3642627, 3642628, G06F 922, G06F 9302, G06F 940

Patent

active

050348795

ABSTRACT:
A processor is disclosed having two levels of subinstructions, with the processor data bus being selectable as either a 16 bit or 32 bit wide bus under nanoprogram control.

REFERENCES:
patent: 3839705 (1974-10-01), Davis et al.
patent: 3859636 (1975-01-01), Cook
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4342078 (1982-07-01), Tredennick
patent: 4466055 (1984-08-01), Kinoshita et al.
patent: 4586130 (1986-04-01), Butts, Jr. et al.

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