Programmable current-sensing circuit providing discrete step...

Details Programmable current-sensing circuit providing discrete step... Programmable current-sensing circuit providing discrete step...

2002-11-26

2004-03-02

Riley, Shawn (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S283000

Reexamination Certificate

active

06700365

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved controllably switched current mirror-based, current-sensing and correction circuit that provides programmable, discrete step compensation for temperature variations of an output switching MOSFET of a buck mode DC—DC converter.
BACKGROUND OF THE INVENTION
Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (DC) power sources, such as a buck-mode, pulse width modulation (PWM) based, DC—DC converter of the type diagrammatically shown in FIG.
1
. As shown therein, a controller
10
supplies a PWM signal to a (MOSFET gate) driver
20
, for controlling the turn-on and turn-off of a pair of electronic power switching devices, to which a load is coupled. In the illustrated DC—DC converter, these power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device
30
, and a lower (or low side) power NFET device
40
, having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).
The upper NFET device
30
is turned on and off by an upper gate switching signal UGATE being applied to its gate from driver
20
, and the lower NFET device
40
is turned on and off by a lower gate switching signal LGATE from driver
20
. A common node
35
between the upper and lower NFETs is coupled through an inductor
50
(which may typically comprise a transformer winding) to a load reservoir capacitor
60
coupled to a reference voltage terminal (GND). A connection
55
between inductor
50
and capacitor
60
serves as an output node from which a desired (regulated) DC output voltage VOUT is applied to a LOAD
65
(shown as coupled to GND).
The output node connection
55
is also fed back to error amplifier circuitry (not shown) within the controller, the error amplifier being used to regulate the converter's output DC voltage relative to a reference voltage supply. In addition, the common node
35
is also coupled to current-sensing circuitry
15
within controller
10
, in response to which the controller adjusts the PWM signal, as necessary, to maintain the converter's DC output within a prescribed set of parameters.
For this purpose, the controller may incorporate a current-sensing circuit of the type described in U.S. Pat. No. 6,246,220, entitled: “Synchronous-Rectified DC to DC Converter with Improved Current Sensing,” issued Jun. 12, 2001, by R. Isham et al, assigned to the assignee of the present application and the disclosure of which is incorporated herein. As described therein, the controller monitors the source-drain current flowing through the lower NFET
40
by way of a current-sensing or scaling resistor
37
electrically interconnected between node
35
and a current-sensing circuit
15
.
The current-sensing circuit is operative to monitor the current I
SENSE
flowing through scaling resistor
37
. This current is the product of the output current I
OUT
flowing from the common node
35
to the inductor 50 times the ratio of the ON-resistance R
DS40ON
of the lower NFET
40
to the resistance R
37
of the scaling resistor
37
, and is thus proportionally representative of the output current I
OUT
. The load current I
L
, namely the current I
50
flowing through the inductor
50
, is substantially equal to the output current I
OUT
minus the current I
SENSE
flowing through the scaling resistor
37
.
As the ratio of R
DS40ON
to R
37
is typically relatively small, the current I
SENSE
will be substantially smaller than the output current I
OUT
, so that the output current I
OUT
and the load current I
L
will have substantially similar magnitudes, making I
SENSE
representative of load current. The resistance of the scaling resistor
37
is selected to provide a prescribed value of current flow for the values of load current I
L
and/or the value of the ON-state resistance R
DS40ON
of the lower NFET
40
. Thus, the sensitivity or magnitude of, for example, voltage droop, current limiting or trip, and current balancing incorporated into the DC/DC converter is effectively ‘scaled’ by selecting resistor
37
relative to the value of the on-state resistance R
DS40ON
of the lower NFET
40
. The voltage drop across the on-state resistance R
DS40ON
of the lower NFET
40
(usually negative) is accommodated in the converter without a negative voltage supply. In addition, as the ON-resistance R
DS40ON
of the lower NFET
40
varies with temperature, scaling resistor
37
may be replaced with a network including a positive temperature coefficient thermistor that has a temperature coefficient which offsets the behavior of NFET
40
.
As shown in greater detail in
FIG. 2
, the controller's current-sensing circuit
15
comprises a sense amplifier
200
having a first, non-inverting (+) input
201
coupled to a controller SENSE− port
11
, and a second, inverting (−) input
202
coupled to a controller SENSE+ port
12
. The SENSE− port
11
is coupled to the grounded termination of NFET
40
, while the SENSE+ port
12
is coupled through scaling resistor
37
to common node
35
. The sense amplifier
200
has its output
203
coupled to the gate
213
of an NFET
210
, whose drain-source path is coupled between the SENSE+ port
12
and input terminal
221
of a current mirror
220
. The current mirror
220
includes a diode-connected input PFET
230
having its drain and gate coupled in common to input terminal
221
and its source coupled to voltage supply rail VCC. The gate of PFET
230
is coupled in common to the gate of current mirror PFET
240
, the source of which is coupled to the supply rail VCC and the drain of which is coupled to an output terminal
222
.
In operation, the sense amplifier
200
and NFET
210
(which serves as a controlled impedance) are operative to continuously drive the controller's SENSE+ port
11
toward ground potential. This forces the end of the current feedback resistor
37
which is connected to controller SENSE+ port
12
to be at ground potential and the end connected to common node
35
to have a negative voltage. The negative voltage at common output node
35
will be equal to the product of the output current I
OUT
and the on-state resistance R
DS40ON
between the drain and source of the lower NFET
40
.
Current from the current mirror
220
flows into the drain and out of the source of NFET
210
into the SENSE+ port
12
. Also flowing into the SENSE+ port
12
from the opposite direction is the current I
SENSE
which, as described above, is representative of load current I
L
. In order to maintain the SENSE+ port
12
at ground potential, sense amplifier
200
adjusts the current flowing through NFET
210
and into SENSE+ port
12
to be substantially equal to I
SENSE
. Since I
SENSE
is representative of the load current I
L
, the current flowing through NFET
210
and into SENSE+ port
12
, as controlled by sense amplifier
200
, is also representative of load current I
L
. Current mirror
220
mirrors the sensed current flowing through NFET
210
and couples this current via output port
222
to the controller's error amplifier circuitry that monitors the output node
55
.
The on state resistance RDS
40ON
of the lower NFET
40
may increase by up to forty percent, as the temperature increases in a typical application. If scaling resistor
37
, which couples the common node
35
to the SENSE+ port
12
does not also increase at the same rate as RDS
40ON
, the fed back current will be in error. To correct for this, resistor
37
may be replaced by a network including a positive temperature coefficient thermistor. This may be both complicated and costly.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above-discussed temperature variation problem is successfully addressed by a new and improved current-sensing and correction c

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