Static information storage and retrieval – Addressing – Counting
Reexamination Certificate
2001-02-02
2002-03-26
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Counting
C365S238500, C365S239000
Reexamination Certificate
active
06363032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory devices, and more particularly to a programmable counter circuit for use in memory devices for generating a sequential/interleave address sequence.
2. Description of the Related Art
Computer memory systems utilize various techniques for enhancing performance of the memory system. One such technique is “burst mode” memory access. A typical burst mode access begins when a memory controller applies an initial address within a burst address space to a memory chip in the memory system, and instructs the memory chip to load the address. After a specific, predetermined amount of time (usually 1 or 2 clock cycles), the memory chip responds with the data stored at the initial address. At the next clock cycle, the memory chip outputs data from a next address within the burst address space of the initial address.
Typically, the addresses within the burst address space are accessed sequentially. For example, if the initial address applied to the memory chip is address
0
, on the next clock cycle the data from address
0
is available from the memory chip. Then, on the next single clock cycle, the memory chip delivers data from address
1
, and on the next single clock cycle, the memory chip delivers data from address
2
, and so on. Such incrementing is done by implementing the addresses in a sequence, using a counter to supply the increments. Binary sequential mode refers to counting in a traditional sequence with the numbers represented in a binary format. In a linear mode, the burst counter always counts up. In a non-linear mode, the burst counter either counts up or down, depending on the start address. Improved memory system performance is achieved since data is available on every clock cycle, after the initial address is presented to the memory chips.
FIG. 1
illustrates how a counter circuit is incorporated into a memory device for generating sequential (binary) and interleaved addresses. Circuit
20
includes a memory cell array
22
that receives inputs from row decoders
24
, column decoders
26
, and input buffers
28
. Array
24
, cooperating with sense amplifiers (not shown) generates outputs to output buffers
30
. Input buffers
28
and output buffers
50
are used for data that is to be retrieved from or stored in the array
22
. Decoders
24
and
26
are used to select a unique row and column. Each combination of row and column will address a unique memory cell within the array. Address decoders
24
and
26
receive address lines from the address latch
32
. The address latch
32
can be directly loaded from the input buffers
28
or from a counter
34
. Counter
34
receives a starting count value from input buffers
28
. As a result, a counter circuit such as counter
34
can be used to generate addresses for a memory circuit.
Table 1 below provides a chart for a three bit sequential count sequence for both binary and interleave modes, where a
in
is the least most significant bit of the start address, a
in
2
is the next most significant bit after a
in
, and a
in
3
is the next most significant bit after a
in
2
.
TABLE 1
BINARY/INTERLEAVE ADDRESSING SEQUENCE
Start Address
Sequential (Binary)
Interleave
(a
in
3, a
in
2, a
in
)
addressing
addressing
000
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
001
1,2,3,4,5,6,7,0
1,0,3,2,5,4,7,6
010
2,3,4,5,6,7,0,1
2,3,0,1,6,7,4,5
011
3,4,5,6,7,0,1,2
3,2,1,0,7,6,5,4
100
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
101
5,6,7,0,1,2,3,4
5,4,7,6,1,0,3,2
110
6,7,0,1,2,3,4,5
6,7,4,5,2,3,0,1
111
7,0,1,2,3,4,5,6
7,6,5,4,3,2,1,0
While the binary mode counting progresses in a traditional counting sequence, interleave mode counting may vary significantly, depending on the starting count value. In interleave mode, the first bit (the least most significant bit) will toggle every count increment. The second bit will toggle on every second count increment, i.e., on the second, fourth, sixth, eighth, etc. count increments. The third bit will toggle on very fourth count increment, i.e., on the fourth, eighth, twelfth, etc., count increments.
As processor speeds continue to increase, increased memory access speeds are becoming more important. As such, it is desirous to provide counter circuits for memory devices that can automatically increment the memory address in both a binary and interleave sequence in order to increase the access speed for blocks of sequential data in semiconductor memories.
SUMMARY OF THE INVENTION
The present invention provides a programmable counter circuit for use in semiconductor memories for generating both sequential and interleave address sequences for block data accesses.
In accordance with the present invention, the output and complementary output of the counter for the previous bit are multiplexed to send the proper carry bit information to the toggle input of the counter for the next bit. In interleave mode, the carry bit forces the row/column counter of the memory device to count in an interleave address sequence. In sequential mode, the start address of the memory access is captured and held. Either the output or complementary output of the counter for the previous bit is used to control the counter of the next bit based on the captured start address bit. Operation is similar in row access mode, such that the rows are accessed in a sequential manner. The counter circuits for memory devices according to the present invention can be programmed to automatically increment the memory address in both a binary and interleave sequence in order to increase the access speed for blocks of sequential data in semiconductor memories.
These and other advantages and features of the invention will become more readily apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Nguyen Tan T.
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