Boots – shoes – and leggings
Patent
1985-07-30
1987-08-04
Ruggiero, Joseph
Boots, shoes, and leggings
364140, 364185, 364900, 371 21, 371 29, 371 71, G06F 900, G06F 1100
Patent
active
046850538
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a programmable controller for detecting an abnormal state of an output signal.
A conventional programmable controller performs sequence control such that a sequence program is stored in a memory therein and a relay or the like of an external device is operated in accordance with the sequence program. When a load resistance of the external device, is small, an element, such as a transistor of an output circuit of a programmable controller, may be damaged. When sequence control is continued even though the element of the output circuit is damaged, normal sequence control cannot be performed. A conventional programmable controller does not have a means for checking such a failure.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a programmable controller to eliminate the conventional drawback described above, by detecting an abnormal state of an output signal therefrom and determining an abnormal part in a circuit.
In order to achieve the above object of the present invention, there is provided a programmable controller, wherein a feedback circuit is provided for feeding an output from an output circuit back to an operation device, the output circuit transmitting an output signal from an output memory to an external circuit; input and output signals with respect to the output memory and the output signal from the output circuit are compared with each other; an abnormality of the output circuit is displayed on a display device when the output signal from the output circuit does not coincide with the input signal to the output memory and the input signal to the output memory coincides with the output signal therefrom, and an abnormality of the output memory is displayed on the display device when the output signal from the output circuit does not coincide with the input signal to the output memory and the input signal to the output memory does not coincide with the output signal therefrom.
With the arrangement described above, since the input and output signals with respect to the output memory and the output signal from the output circuit are compared to detect coincidences and an abnormal part in the circuit is displayed on the display device upon detection of a noncoincidence, the abnormality and failure of the output circuit and the output memory which tend to be influenced by an external circuit connected thereto are immediately found, thereby preventing erroneous operation of the programmable controller.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an embodiment the present invention;
FIG. 2 is a circuit diagram of a feedback circuit of the embodiment; and
FIG. 3 is a flow chart for explaining processing in accordance with the embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram of a programmable controller according to an embodiment of the present invention. Reference numeral 1 denotes a computing unit (to be referred to as a CPU hereinafter) having an arithmetic and logic function for determining the state of an output signal upon reception of an input signal, and a display instruction function for causing a CRT 3 to display data in accordance with a program stored in a ROM 5 for sequence control (to be described later). Reference numeral 2 denotes an input circuit for receiving signals from an external limit switch, a proximity switch and switches on an operation panel. Reference numeral 3 denotes a display device for displaying a state of the programmable controller and states of the input and output signals. Reference numeral 4 denotes a key input device for designating a display mode for the CPU 1 and an operation mode of the programmable controller. Reference numeral 5 denotes a ROM for storing a sequence program for determining the operation of a machine as an object of interest. Reference numeral 6 denotes a ROM for receiving the sequence program from the ROM 5 and
REFERENCES:
patent: 4095094 (1978-06-01), Struger et al.
patent: 4118792 (1978-10-01), Struger et al.
patent: 4251883 (1981-02-01), Grants et al.
patent: 4527271 (1985-07-01), Hallee et al.
patent: 4535456 (1985-08-01), Bauer et al.
patent: 4560936 (1985-12-01), Pelowski
patent: 4592053 (1986-05-01), Matsuura
Hattori Kiyoshi
Usuda Eiji
Fanuc Ltd
Ruggiero Joseph
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