Programmable CMOS flip-flop emptying multiplexers

Details Programmable CMOS flip-flop emptying multiplexers Programmable CMOS flip-flop emptying multiplexers

1992-04-16

1992-11-17

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 307270, 3072963, 307243, 307453, H03K 3289, H03K 301

Patent

active

051646129

ABSTRACT:
A CMOS flip-flop circuit that includes master and slave inverter latches, a pass transistor for opening and closing access of the master latch input to an input signal D, and a special driver circuit between the master and slave latches to pull the input of the slave latch either up or down depending on the logic level of the master latch output. The pass transistor and driver circuit are responsive to a control signal, supplied by complementary clock signals or by multiplexers that select either the clock signals or a fixed logic high signal, to activate a conductive path to the inputs of respective master and slave latches. The driver circuit includes four transistors connected, so that first and second transistors are in series and third and fourth transistors are in series, to form two parallel paths from two logic level sources to the slave latch input. First and third transistors are driven by the master latch output, while second and fourth transistors are driven by the control signal to the drive circuit. The two logic level sources connected to the first and third transistors may be fixed logic high and low voltage levels for conventional flip-flop operation or to multiplexers, each selecting either a logic high or a logic low voltage level, for programmable polarity of the flip-flop output. Placing latches enabled by the pass transistor control signal between the multiplexers and the first and third transistors and increasing the selection of the multiplexers to include complementary slave latch output feedback signals provides programmable D-type or toggle flip-flop operation. The multiplexer's nontoggle selection signal may be fixed or dynamically variable through a configuration multiplexer for dynamic polarity of the flip-flop's output.

REFERENCES:
patent: 4700088 (1987-10-01), Tubbs
patent: 5115150 (1992-05-01), Ludwig

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