Programmable clock rate generator

Details Programmable clock rate generator Programmable clock rate generator

1981-01-12

1983-11-01

Gruber, Felix D.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

364703, 377 56, 377114, G06M 300, H03K 2136

Patent

active

044133502

ABSTRACT:
A clock rate generator is described which can be programmed to provide an output clock rate that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter, a programmable memory, reset logic and a clocking control. A standard clock is applied to the counter so that the counter is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory where a pattern of binary ones and zeros are stored. The output of the programmable memory is applied to the clocking control to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter. The multiplier N is determined by the number of output cycles from the clocking control between successive resets of the counter.

REFERENCES:
patent: 3566096 (1971-02-01), Schultheis, Jr.
patent: 3657658 (1972-04-01), Kubo
patent: 3824379 (1974-07-01), Tomisawa et al.
patent: 3909791 (1975-09-01), van den Berg
patent: 3937932 (1976-02-01), Ahlgren
patent: 3970954 (1976-07-01), Even
patent: 4084082 (1978-04-01), Alfke
patent: 4140970 (1979-02-01), Graziano
patent: 4184068 (1980-01-01), Washburn
patent: 4251722 (1981-02-01), Vautier
patent: 4254327 (1981-03-01), Beno et al.

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