Programmable clock manager for a programmable logic device that

Details Programmable clock manager for a programmable logic device that Programmable clock manager for a programmable logic device that

1997-10-15

2000-02-22

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

326 39, H03K 738

Patent

active

060284633

ABSTRACT:
A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.

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