Programmable clock drivers that support CRC error checking...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S147000, C327S544000, C713S323000

Reexamination Certificate

active

10979979

ABSTRACT:
A packaged integrated circuit device includes a nonvolatile memory device and a programmable clock driver circuit therein. The memory device may be provided as an EEPROM device that is disposed on a first integrated circuit substrate and the programmable clock driver circuit may be disposed on a second integrated circuit substrate. The programmable clock driver circuit includes a control circuit and a clock generator therein. The control circuit is configured to detect an error(s) in configuration data that is used by the programmable clock driver circuit. This configuration data is read from the nonvolatile memory and stored in volatile program registers during program restore operations. The control circuit is further configured to automatically idle the clock generator in response to detecting the error in the configuration data. This automatic idling of the clock generator may include operations to set the clock generator at a default setting (e.g., minimum frequency), which applies to all output banks of the driver circuit.

REFERENCES:
patent: 5485490 (1996-01-01), Leung et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5684434 (1997-11-01), Mann et al.
patent: 5877656 (1999-03-01), Mann et al.
patent: 6111445 (2000-08-01), Zerbe et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6215689 (2001-04-01), Chhor et al.
patent: 6271702 (2001-08-01), Stansell
patent: 6329859 (2001-12-01), Wu
patent: 6330679 (2001-12-01), Conary et al.
patent: 6359486 (2002-03-01), Chen
patent: 6384653 (2002-05-01), Broome
patent: 6388478 (2002-05-01), Mann
patent: 6433645 (2002-08-01), Mann et al.
patent: 6466098 (2002-10-01), Pickering
patent: 6492852 (2002-12-01), Fiscus
patent: 6509773 (2003-01-01), Buchwald et al.
patent: 6525584 (2003-02-01), Seo et al.
patent: 6539072 (2003-03-01), Donnelly et al.
patent: 6597212 (2003-07-01), Wang et al.
patent: 6678832 (2004-01-01), Gotanda
patent: 6691215 (2004-02-01), Mirov et al.
patent: 6768358 (2004-07-01), Birk et al.
patent: 2005/0242853 (2005-11-01), Kwack et al.
Rabaey, Jan M., “Synchronization at the System Level,” Digital Integrated Circuits, A Design Perspective, Prentice-Hall, Inc., pp. 540-543.
“High-Speed Multi-Phase PLL Clock Buffer,” Cypress Semiconductor Corporation, Revised Jul. 25, 2003, 14 pages.
IT Clock Management Products Family, Aug. 2002, Admitted Prior Art, 4 pages, not available.
Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,” IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1491-1496, not ava.
Cypress Semiconductor Corporation, “High Speed Multi-Phase PLL Clock Buffer,” RoboClockII™ CY7B994V, CY7B993V, Aug. 8, 2000, 14 pages, not ava.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable clock drivers that support CRC error checking... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable clock drivers that support CRC error checking..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable clock drivers that support CRC error checking... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3729725

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.