Programmable clock divider

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

Reexamination Certificate

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Details

C327S117000, C377S047000

Reexamination Certificate

active

08004319

ABSTRACT:
In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.

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patent: 1 612 942 (2006-01-01), None

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