Programmable chip tester having plural pin unit buffers which ea

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371 16, 371 20, 371 27, 324 73R, 324 73PC, 324 73AT, 364481, 364490, G06F 1100, G01R 3128

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045176612

ABSTRACT:
A test system for testing circuits in integrated circuit chips includes a host computer for controlling the test system, and a plurality of blocks operable in parallel and each including a controller, storage for test programs and test data, and plurality of electronic units or pin electronics cards, one unit being associated with one of the pins of a device under test. Each of the electronic units include timing circuitry for timing its associated pin independent of the timing of any other electronics unit.

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