Programmable ceramic high performance custom package

Details Programmable ceramic high performance custom package Programmable ceramic high performance custom package

1988-06-27

1990-11-20

James, Andrew J.

357 71, 357 70, H01L 2302

Patent

active

049722530

ABSTRACT:
Ceramic packages for encapsulating integrated circuit (IC) chips are made of layers which are laminated together in a co-firing process. A signal layer includes leads electrically connecting external pins with the chip itself. Other layers supply ground and power to the chip by way of the signal layer. The layers are designed so that when a new chip is to be introduced, only one layer of the package, called a "VIA layer," needs to be re-designed for the new chip. The VIA layer is programmed with connections or "vias" at specific locations between the signal layer and a power or ground layer above or below the signal layer. The "vias" are conductive dots that extend through the VIA layer. The layer opposite the signal layer on the other side of the VIA layer contains "internal supply and ground bars" that are electrically connected to internal supply and ground layers. Therefore, selective positioning of the vias enables each signal lead in the signal layer to be selectively connected to internal power or ground. The internal supply and ground bars are aligned transversely with respect to the signal lead, and are close to the chip to minimize the inductance of the connections. For custom chip designs, the programmed VIA layer enables certain bonding areas to be preassigned to power and ground while permitting the circuit designer to freely select the assignment of the external pins.

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Hoss et al., "Unique Design of Pin Grid Array Package Accommodates Multiple VLSI Chip Sources," Abstract, National Bureau of Standards IEEE-CHMT Society, VLSI & GAAS Packaging Workshop, Sheraton Imperial Hotel, Research Triangle Park, N.C., Sep. 14-16, 1987.

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