Programmable capacitance delay element having inverters controll

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

307443, 307594, 307597, H03K 513, H03K 1920

Patent

active

052836312

ABSTRACT:
A delay element for fine tuning the position in time of timing edges of an input signal, comprising a first and a second inventer, each comprising a data input, a control input and a data output. The delay element further comprises a node comprised of a connection between the data output of the first inverter and the data input of the second inverter. An adjustable control voltage is included for applying a biasing voltage to the first and second control inputs to thereby control the amount of charge supplied to the node. Finally, the variable capacitance means is connected to the node for applying finite amounts of capacitance to the node to delay and thereby fine tune in time the timing edges of the input signal propagating from the first inverter to the second inverter.

REFERENCES:
patent: 3660647 (1972-05-01), Pryor, Jr.
patent: 4028979 (1977-06-01), Luce
patent: 4266197 (1981-05-01), Breithaupt
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4489342 (1984-12-01), Gollinger et al.
patent: 4499387 (1985-02-01), Konishi
patent: 4504749 (1985-03-01), Yoshida
patent: 4626716 (1986-12-01), Miki
patent: 4638191 (1987-01-01), Baumgartner et al.
patent: 4644184 (1987-02-01), Miyawaki et al.
patent: 4700089 (1987-10-01), Fujii et al.
patent: 4714924 (1987-12-01), Ketzler
patent: 4754164 (1988-06-01), Flora et al.
patent: 4845390 (1989-07-01), Chan
patent: 4894791 (1990-01-01), Jiang et al.
patent: 4899071 (1990-02-01), Morales
patent: 4922140 (1990-05-01), Gahle et al.
patent: 4947064 (1990-08-01), Kim et al.
patent: 5012141 (1991-04-01), Tomisawa
patent: 5028824 (1991-07-01), Young
patent: 5081380 (1992-01-01), Chen
"A 10-ps Resolution, Process-Insensitive Timing Generator IC", Otsuji et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 19, 1989, pp. 1412-1418.
"Integrated Pin Electronics for VLSI Functional Testers", Gasbarro et al., IEEE Journal of Solid State Circuits, vol. 24, No. 2, Apr. '89, pp. 331-337.
"Bt605 125 MHz 10KH ECL Compatible Programmable Timing Edge Vernier" Brooktree Corp. 9950 Barnes Canyon Rd., San Diego, Calif. 92121, pp. 9-17-9-28.
"Integrated Pin Electronics For A VLSI Test System", Branson et al., IEEE 1988 International Test Conference, pp. 23-27.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable capacitance delay element having inverters controll does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable capacitance delay element having inverters controll, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable capacitance delay element having inverters controll will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-583140

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.