Programmable burst data transfer apparatus and technique

Details Programmable burst data transfer apparatus and technique Programmable burst data transfer apparatus and technique

1988-06-24

1992-07-28

Lee, Thomas C.

Boots, shoes, and leggings

3649646, 3649492, 3649582, 3649529, 364DIG2, G06F 1328

Patent

active

051346990

ABSTRACT:
A data processing system having a processor capable of initiating a request for a burst of data transfer and a memory. A memory controller is connected to the processor and to the memory. The controller includes a burst count register having a value stored therein representative of the maximum number of data transfers allowed per burst. Also in the memory controller is a column latch/counter having stored therein a value representative of a column latch address. The column latch/counter is capable of incrementing the address. Finally, included in the memory controller is a programmable mask for specifying bits in the column latch/counter to be compared to corresponding bits in the burst count register.

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