Programmable bandwidth during start-up for phase-lock loop

Details Programmable bandwidth during start-up for phase-lock loop Programmable bandwidth during start-up for phase-lock loop

2006-04-04

2006-04-04

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C331S017000, C331S016000

Reexamination Certificate

active

07023250

ABSTRACT:
A phase lock loop PLL which includes an oscillator having an oscillator signal whose frequency is related to a received error correction signal and phase frequency detector receiving and comparing the oscillator signal and a reference signal from a master circuit and generating the error correction signal based on the phase difference of the oscillator signal and the reference signal. A filter, including a capacitor, connects the error correction signal from the phase-frequency detector to the oscillator. A rate selector monitors a charge on the capacitor and controls the rate of error connection signals as a function of the charge on the capacitor.

REFERENCES:
patent: 5475326 (1995-12-01), Masuda
patent: 5694062 (1997-12-01), Welch et al.
patent: 5929677 (1999-07-01), Murata
patent: 6229362 (2001-05-01), Choi
patent: 6853252 (2005-02-01), Dickmann
patent: 408307257 (1996-11-01), None

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