Programmable arithmetic logic unit

Details Programmable arithmetic logic unit Programmable arithmetic logic unit

1982-03-12

1984-06-12

Malzahn, David H.

Boots, shoes, and leggings

364749, G06F 750, H03K 1920

Patent

active

044545894

ABSTRACT:
A programmable arithmetic logic unit for performing high speed bit sliced, pipelined computations at very low power is fabricated as an LSI component using CMOS/SOS technology. It is microprogrammable and operates in conjunction with a fast microprogram store program memory and controller. Dual input ports which supply data from eight sources are latched and operated on while new data is simultaneously fetched. Instruction bits shift data in either port left or right, select complements and select an operand between device input and output data in one port. The data processed in each port is compared and is added to provide a latched tri-state output to an external device.

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patent: 4075704 (1978-02-01), O'Leary
patent: 4110822 (1978-08-01), Porter et al.
Kogge, "The Microprogramming of Pipelined Processors", IBM Federal Systems Division, Owego, N.Y., pp. 63-69.

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