Programmable architecture and methods for motion estimation

Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal

Reexamination Certificate

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C375S240170

Reexamination Certificate

active

06965644

ABSTRACT:
A programmable motion estimator includes one dual ported memory for storing an image block, the prediction error, and a temporary block used in interpolation, and a pixel-group random access dual ported memory for storing a search window. The two ports of the two memories are selectively applied to an arithmetic logic unit, or ALU, through a multiplexer. One output of the ALU provides an absolute difference, which is furnished to a tree adder. Another output of the ALU provides an average value or a difference value, as selected, which is routed to the inputs of the image memory and the search memory. In motion vector searching, the ALU performs pixel absolute difference arithmetic using the pixel groups from the image memory and from the search memory, and determines a sum of absolute differences in the tree adder. In half pixel interpolation, the ALU performs pixel averaging arithmetic using pixel groups from the search memory, and writes back to the search memory. In quarter pixel interpolation, the ACU performs pixel averaging arithmetic using pixel groups from the image and search memories, and writes back to the search memory. In some quarter pixel interpolations, temporary interpolated blocks from the image memory are used to interpolated quarter pixel blocks. These temporary blocks are obtained by pixel averaging in the ALU using pixel groups from the search memory. In error prediction determination, the ALU performs pixel subtraction using the pixel groups from the image memory and from the search memory, and writes back to the image memory.

REFERENCES:
patent: 4864393 (1989-09-01), Harradine et al.
patent: 5083202 (1992-01-01), Parke
patent: 5216501 (1993-06-01), Ando
patent: 5379351 (1995-01-01), Fandrianto et al.
patent: 5790712 (1998-08-01), Fandrianto et al.
patent: 6124882 (2000-09-01), Voois et al.
patent: 6441842 (2002-08-01), Fandrianto et al.
Yang et al, “A Family of VLSI Designs for the Motion Compensation Block-Matching Algorithm”, IEEE Transactions on Circuits and Systems, vol. 36, No. 10, pp. 1317-1325, Oct. 1989.

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